From 0c721fa0125d628ba4f3b6120f5ac9d27ed124ba Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?J=C3=BCrgen=20Buchm=C3=BCller?= Date: Fri, 17 Mar 2017 09:56:33 +0100 Subject: [PATCH] flightgear: fix musl --- .../patches/musl-fix_execinfo_h.patch | 22 +++++++++++++++++++ .../patches/musl-fix_feenableexcept.patch | 11 ++++++++++ 2 files changed, 33 insertions(+) create mode 100644 srcpkgs/flightgear/patches/musl-fix_execinfo_h.patch create mode 100644 srcpkgs/flightgear/patches/musl-fix_feenableexcept.patch diff --git a/srcpkgs/flightgear/patches/musl-fix_execinfo_h.patch b/srcpkgs/flightgear/patches/musl-fix_execinfo_h.patch new file mode 100644 index 00000000000..d6fc140d42e --- /dev/null +++ b/srcpkgs/flightgear/patches/musl-fix_execinfo_h.patch @@ -0,0 +1,22 @@ +--- src/Main/bootstrap.cxx 2017-03-17 09:52:07.474706542 +0100 ++++ src/Main/bootstrap.cxx 2017-03-17 09:53:40.361793507 +0100 +@@ -141,7 +141,7 @@ + } + #endif + +-#if defined(__GNUC__) ++#if defined(__GNUC__) && defined(__GLIBC__) + #include + #include + void segfault_handler(int signo) { +@@ -244,8 +244,10 @@ + + signal(SIGPIPE, SIG_IGN); + # ifndef NDEBUG ++# ifdef __GLIBC__ + signal(SIGSEGV, segfault_handler); + # endif ++# endif + #endif + + _bootstrap_OSInit = 0; diff --git a/srcpkgs/flightgear/patches/musl-fix_feenableexcept.patch b/srcpkgs/flightgear/patches/musl-fix_feenableexcept.patch new file mode 100644 index 00000000000..2b967478e4b --- /dev/null +++ b/srcpkgs/flightgear/patches/musl-fix_feenableexcept.patch @@ -0,0 +1,11 @@ +--- src/FDM/JSBSim/JSBSim.cpp 2017-03-01 21:06:31.000000000 +0100 ++++ src/FDM/JSBSim/JSBSim.cpp 2017-03-17 09:49:13.115544107 +0100 +@@ -287,7 +287,7 @@ + _clearfp(); + _controlfp(_controlfp(0, 0) & ~(_EM_INVALID | _EM_ZERODIVIDE | _EM_OVERFLOW), + _MCW_EM); +-#elif defined(__GNUC__) && !defined(sgi) && !defined(__APPLE__) ++#elif defined(__GNUC__) && !defined(sgi) && !defined(__APPLE__) && defined(__GLIBC__) + feenableexcept(FE_DIVBYZERO | FE_INVALID); + #endif +